MP2005 800ma high psrr, uldo linear regulator MP2005 rev. 0. 92 www.monolithicpower.com 1 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. the future of analog ic technology descri ption the mp200 5 is a micro power, ultra low-dropout ldo linear regulator. it has a 1.0v to 5.5v input voltage range and can regulate the output voltage from as low a s 0.5v. the MP2005 can supply up t o 800ma of load curr ent with a typical dropout voltage of 90mv. it requires a bias supply (2.7v to 5.5 v ) separate from v in to run the int e rnal reference and ldo drive circuitry. th e output cur r ent comes directly from the input v o ltage sup p ly for hig h efficiency regulation. the 0.5v in ternal refere nce voltage allows the o u tput to be programme d to a wide range of voltages (0.5v to 4v). a low bias current of 100a makes the MP2005 ideal for use in battery-powered a pplication s . the bias supply v bias can be dire ctly applied from the ba ttery while v in is powered from the high efficiency buck regulator (or other secondary supply). this reduces output noise and the size of the deco upling capa citor. other features of MP2005 inclu de thermal overload an d current limit protection, stability with ultra low esr ceramic capacito r s as low as 1 f, and fa st transient response. t he MP2005 is available in a 8-pin qfn (2 mm x 3 m m) package. features ? wide 1.0v to 5.5v input voltage range ? stable with 1 f cera mic capacitor ? ultr a-l o w dr o pou t (u ldo) v o lt ag e: 90mv @800ma ? 2% accurat e output voltage ? adjustable output ran ge of 0.5v to 4v ? high psrr o 65db at 1khz o 48db at 1mhz ? better than 0.0005%/ma load regulation ? stable with low-esr output capacitors ? low 100 a ground current ? internal the rmal protection ? current limit protection ? 1a typical quiescent current at shutdown appli c ations ? low current regulators ? low power handheld devices ? battery powered systems ? cellular phones ? portable electronic equipment ? post regulation for switching power supplies ? power supp lies ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application http://
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 2 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) MP2005dd qfn8 (2mm x 3mm) n3 ?40 c to +85 c * for tap e & reel, ad d suf f ix ?z (e.g. MP2005 dd?z) for rohs co mpliant pa ckaging, ad d su ffix ?lf (e.g. MP2005 dd? l f?z ) package reference top view in bias nc gnd 1 2 3 4 out fb nc en 8 7 6 5 exposed pad on backside connect to gnd absolute m a xi mum ratings (1) v bias , v in to gnd ............................ ?0.3v to +6v fb, en to gnd ................................ ?0.3v to 6v out ................................................. ?0.3v to 6v continuous power dissipation (t a = +25c) (2) ................................................................... 2.3w junction te mperature ............................... 150 c lead temperature .................................... 260 c storage temperature ............. ?65c to +150 c recommended operating conditions (3) input voltag e v in ............................. 1.0v to 5.5v input voltag e v bias .......................... 2.7v to 5.5v output voltage ................................ 0.5v to 4.0v load current ........................... 800ma maxi mum operating temperature............. ?40 c to +85 c thermal resistance (4) ja jc qfn8 (2 mm x 3mm) ............... 55 ...... 12 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction temperatu r e t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the maximu m allow a ble con t inuous po w e r di ssipation at an y ambient tem peratur e is calculated b y p d (max)=(t j (max)- t a )/ ja . excee d ing the maximum allow able po wer dissipation w ill cause ex cessive die temperature, and the reg u l ator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarante ed to fu nction outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 3 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. electri c al characteristi cs v in = 1.5v, v bi a s = 3.6v, v out = 1.2v, c2 =4.7f, c3 = 1f , t a = +25 c, unless otherw ise no ted. parameter sy mbol conditio n min t y p max units v in operating voltage 1.0 5.5 v v bias operating voltage 2.7 5.5 v v in operating current v out = 1.2v 4 10 a v bias operating cu rrent i out = 10a, v out = 1.2v 100 150 a i out = 1ma to 800ma 0.490 0.500 0.510 fb regul atio n voltage ?40 c t a +85 c, v out = 0.5 v 0.487 0.500 0.512 v dro pout volta ge i out = 800ma , v bia s = 3.6v 70 90 mv v in line regulation i out = 1ma , v in = 1.0v to 5.5v v bias = 3.6v v out = 0.5v 0.002 %/v v bias line regulation i out = 100ma , v bias = 2.7v to 5.5v v out = 0.5v v in = 1.5v 0.04 %/v load reg u lat i on i out = 1ma to 800ma 0.0005 %/ma psrr v in > v out + 0.5v, c2 = 1 0 f, v in (ac) = 100mv, f = 1mhz 48 db en input hig h voltage 1.3 v en input low voltage 0.8 v en input bias current v en = 1.2v ?1 +1 a therm a l prot ection 155 c therm a l prot ection hysteresi s 30 c gn d cu rr ent i load = 500m a 110 150 a pin functio n s pin # nam e des c ription 1 in power source input. bypas s in to g n d with a 1f or greate r ca pa citor. 2 bias bias voltage. bypass to g nd with a 1 f capa cito r (o r gre a ter ) 3, 6 nc no conn ect. 4 gnd ground. 5 en enable input. drive en high to turn on the MP2005, drive en low to turn it off. for automatic sta r tup, co nne ct en to bias. 7 fb feedback inp u t. conne ct a resi stive voltage di vide r from out to f b to set the output voltage. out feedba ck thresh old is 0.5 v . 8 out regu lator o u tput. out is the output of the linea r re gu lator. bypass out to g nd with a 1f or g r eate r cap a cito r.
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 4 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. typical perfo r manc e characteristics c1=c3=2.2uf, c2=4.7uf, v en =v bias =3.6v, t a =25oc, unless otherwise noted 0 1.000 1.001 1.002 1.003 1.004 1.005 200 400 800 1000 600 0 200 400 800 1000 600 0 200 400 800 1000 600 load current (ma) load current (ma) load current (ma) load regulation load regulation load regulation 3.0 4.2 3.6 3.20 3.25 3.30 3.35 3.40 5.4 4.8 6.0 output vol t age (v) output vol t age (v) input vol t age (v) input vol t age (v) output voltage (v) output voltage (v) output voltage (v ) input vol t age (v) line regulation line regulation line regulation psrr(db) psrr vs. v in dropout vol t age (mv) psrr (db) 0 0 20 40 60 80 100 120 800 200 1000 400 600 0.1 1000 1 10000 10 100 1.0 2.0 1.000 1.002 1.004 1.006 1.008 1.010 2.45 2.47 2.49 2.51 2.53 2.55 3.0 4.0 5.0 6.0 -10 0 10 20 30 40 50 60 70 80 90 2.1 2.2 2.3 2.4 2.6 2.5 2.0 2.8 3.6 4.4 5.2 6.0 1.2 0 10 20 30 50 40 1.4 1.6 1.8 2.0 2.2 2.4 2.6 load current (ma) frequency (khz) input vol t age (v) v oltage dropout psrr vs. frequency v in =2.5v v bias =4.5v v in =1.5 v v out =1.2v i out =0.1a v in =1.5 v v out =1.2v i out =0.1a f=1mhz v bias =3.5v i out =50ma i out =100ma v bias =4.5v i out =100ma i out =100ma v bias =5v 3.28 3.29 3.30 3.31 3.33 3.32 v bias =3.5 v v in =3v v in =2.5v v bias =4.5 v v in =1.5v v in =3.6v v bias =5 v
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 5 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. typical perfo r manc e characteristics (continued ) c1=c3=2.2 uf, c2=4.7uf, v en =v bi a s =3.6v, t a =25oc, unless otherw is e noted dropout voltage (mv) -40 20 24 28 32 36 40 feedback vol t age (mv) 500 501 502 503 504 505 output vol t age (mv) 1.200 1.202 1.204 1.206 1.208 1.210 60 -15 85 10 35 -40 60 -15 85 10 35 -40 60 -15 85 10 35 dropout v oltage vs. t emperature feedback v oltage vs. t emperature output v oltage vs. t emperature v out =1.2v i out =0.3a v out =1.2v v in =1.5v i out =0.3a v in =1.0v i out =1ma 10 100 1000 10000 100000 output noise (nv/ hz ) 200 0 400 600 800 1000 1200 frequency (hz) output noise vs. frequency v out =3.3v v in =v bias =5.4v i out =10ma
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 6 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. typical performanc e characteristics (continued) c1=c3=2.2uf, c2=4.7uf, v en =v bias =3.6v, v in =3.6v, t a =25oc, unless otherwise noted
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 7 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. block diagram -- + reference 2 5 4 bias en gnd 1 8 7 in out fb 0.5v fil ter and soft -st ar t ocp -- + figure 1?block diagram of super low drop out regulator
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 8 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. appli c ation information setting the output voltage the MP2005 has an adjustable output voltage, set by using a resistive voltage divider from the output voltage to fb pin. the voltage divider divides the output voltage down to the feedback voltage by the ratio: 2 r 1 r 2 r v v out fb + = where v fb is the feed back thresh old voltage (v fb = 0.5v), and v out is the output voltage. thus the out put voltage is: 2 r 2 r 1 r 5 . 0 v out + = r2 can be as high as 10 0k ? , but a typical value is 10k ? . using that value, r1 is det ermined by: ? ? ? ? ? ? ? ? ? = fb fb out v v v 2 r 1 r for exampl e, for a 1.8 v output voltage, r2 is 10k ? , and r1 is 26k ? . you can select a standard 26 k ? (1%) resistor for r1. the following table lists the sele cted r1 for various output voltages. tabl e 1 ? ad ju s t ab le ou tpu t vol t ag es r1 val u es v out (v) r1 (k ? ) r2 (k ? ) 1.25 15 1.5 20 1.8 26 2 30 2.5 40 2.8 46 3 50 3.3 56 4 70 10 bias input the b i as i nput is de signed for low dro p applica t ion. the bias pin must be a t leas t 2 . 7 v , and at l east 1.5v highe r than the o u tput . if v in suppl y vol t a ge mee t s t hese requi rements, the bias pi n can be tie d t o v in . feed forw a rd capacitor for stability, it needs a 10nf capacitor parallel with r1. the ceramic type ca pacitor, will provide the best perfor m ance.
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r MP2005 rev. 0. 92 www.monolithicpower.com 9 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. pcb la y o u t guide pcb layout is very important to achieve good regulatio n, ripple rejection, tran sient respo n se and thermal performance. it is highly recommended t o duplicate evb layout f o r optimum performance. if change is necessary, please follo w these guidelines and take figure 2 for reference. 1) input and o u tput bypass ceramic capacitors ar e suggested to be put close to the i n pin and out pin respectively. 2) ensure all feedback connection s are short and direct. place th e feedback resistor s and compensation components as close to the chip a s possib l e. 3) connect in, out and especially gnd respe c tively to a large copp er area to cool the chip to improve thermal performance and lo ng-term reliability. c1 c2 c3 r3 r1 r2 v in v out c4 v bias en top la y e r bottom la y e r figure 2?pcb la y out
MP2005 ? 8 00ma, high psrr,ul do linear regulat o r notice: t he i n formatio n in this docum ent is subject to chang e w i t h o u t notice. please c ontact m ps for current specifi c ations. users sho u ld w a rrant a nd g u a rante e that thi r d part y inte lle ctual prop ert y rights ar e n o t infring ed u pon w h e n inte grati ng mps prod ucts into a n y app licati on. mps w i ll n o t assume an y l e g a l resp onsi b il ity for an y sa id a pplic atio ns. MP2005 rev. 0. 92 www.monolithicpower.com 10 5/5/2010 mps proprietar y information. un a u t horized photoc op y and duplication prohibited. ? 2010 mps. all rights reserved. package informati o n qfn8 (2mm x 3mm)
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